PRISM: A Programming-Free On-Device Multi-task Adaptation Framework for ReRAM-based Computing-in-Memory Accelerator

Yihang Zuo, Wanhao Yu, Asmer Ali, Li Yang, Deliang Fan

ACM/IEEE International Conference on Computer-Aided Design (ICCAD) 2026

Resistive random-access memory (ReRAM) crossbar arrays, known for high parallelism and energy efficiency, have been widely adopted to accelerate neural network (NN) inference. However, enabling on-device training on ReRAM-based accelerators remains challenging due to their high programming energy, voltage, and limited endurance. In this paper, we propose PRISM, a novel ReRAM programming-free on-device multi-task adaptation framework, enabling task adaptation via novel lightweight task-specific attribute prompt generation and step mask learning, with ultra-lightweight hardware and memory overhead, and eliminating energy-intensive ReRAM cell reprogramming. Specifically, PRISM first builds a task-specific attribute library using the frozen backbone model deployed in ReRAM by clustering representative features from a subset of the target new task dataset. Then, it computes the correlation between each input and the attribute library to generate a prefix prompt embedding. In addition, PRISM learns a novel crossbar column-wise and hardware-friendly step mask for each new task while keeping the backbone fixed. Extensive experiments show that the total training energy of PRISM is only 0.03% of that of all-parameter fine-tuning, with only 3.9% area overhead. Moreover, compared with the state-of-the-art multi-task adaptation method, PRISM improves accuracy by an average of 3.6% in the DeiT transformer model for standard multi-task adaptation datasets.

Dominant-Layer ZO: A Single Layer Dominates Zeroth-Order Fine-Tuning of LLMs

Wanhao Yu, Ziyan Wang, Zheng Wang, Abeer Matar Almalky, Yihang Zuo, Shuteng Niu, Sen Lin, Adnan Siraj Rakin, Deliang Fan, Li Yang

ArXiv 2026

Zeroth-order (ZO) optimization enables memory-efficient fine-tuning of large language models (LLMs) using only forward passes, but it remains unclear how useful adaptation is distributed across layers. In this work, we reveal a surprising phenomenon: ZO fine-tuning is sharply dominated by a single decoding layer. Across multiple LLM families and downstream tasks, fine-tuning this dominant layer alone consistently matches or even exceeds full-model ZO fine-tuning. We further show that the dominant layer is task-agnostic but model-specific, and can be identified before training through a simple inference-only analysis of activation outliers. Specifically, the dominant layer consistently aligns with the first activation-outlier layer in the pre-trained model. To explain this phenomenon, we analyze how perturbation effects propagate under ZO optimization. We find that the dominant layer combines two key properties: high perturbation sensitivity and early placement in the residual stream, allowing perturbation-induced effects to propagate and accumulate through remaining subsequent decoding layers. As a result, this layer produces disproportionately strong and stable optimization signals under forward-only updates. Extensive experiments on LLaMA2-7B and Qwen3-8B across nine benchmarks show that dominant-layer ZO fine-tuning improves average performance over full-model MeZO and LoRA-based ZO fine-tuning while achieving up to 4.52 training speedup.

[paper]

Harmony: A Hardware-Mapping Co-Exploration Framework for Hybrid CIM-based Vision Transformer Accelerator

Yihang Zuo, Zexin Fu, Cong Wang, Yuchao Wu, Jiayi Huang, Yuzhe Ma

International Symposium on Quality Electronic Design (ISQED) 2026

🏆 Best Paper Award

Computing-in-memory (CIM) architectures have successfully enhanced convolutional neural network (CNN) performance, but the automation of high-performance CIM-based transformer accelerators is still challenging. Specifically, the design space of hardware design and mapping is extremely large due to the complex model structure and data flow. To address this problem, we propose Harmony, a hardware and mapping co-exploration framework to optimize the hybrid CIM-based vision transformer accelerator. We define a universal design space representation for implementing vision transformers in CIM-based accelerators that support hybrid and heterogeneous features. The corresponding design space comprises the hardware configuration of CIM macros and their spatial mapping scheme. Furthermore, we propose the knowledge-guided grid search (KGGS) algorithm and improved genetic algorithm (IGA) to boost exploration efficiency. The orthogonal experiment and dominance analysis of KGGS could obtain the exploration probabilities of different parameters and ensure its stability, while the unique order crossover and swapping mutation of IGA could retain relative order to avoid legalization processes during the iteration.

[paper] [pdf]

Optimizing Heterogeneous Compute-in-Memory with Hybrid Dataflow and In-Network Reduction for Vision Transformer

Zexin Fu, Yihang Zuo, Yuzhe Ma, Jiayi Huang

International Symposium on Low Power Electronics and Design (ISLPED) 2025

Vision Transformers (ViTs) have shown remarkable success in computer vision tasks, but their computational demands pose significant challenges for efficient deployment. This paper presents an optimization framework for heterogeneous Compute-in-Memory (CIM) architectures that leverages hybrid dataflow and in-network reduction techniques to accelerate ViT inference. Our approach addresses the unique computational patterns of ViTs by combining different dataflow strategies and implementing efficient reduction operations within the CIM network.

[paper] [pdf]

OpenC2: An Open-Source End-to-End Hardware Compiler Development Framework for Digital Compute-in-Memory Macro

Tianchu Dong, Shaoxuan Li, Yihang Zuo, Hongwu Jiang, Yuzhe Ma, Shanshi Huang

Design, Automation & Test in Europe Conference (DATE) 2024

Compute-in-Memory (CIM) has emerged as a promising paradigm to address the memory wall problem in modern computing systems. However, the lack of comprehensive toolchains for CIM macro development hinders its widespread adoption. This paper presents OpenC2, an open-source end-to-end hardware compiler development framework specifically designed for digital CIM macros. OpenC2 provides a complete toolchain from high-level algorithm descriptions to optimized CIM macro implementations, enabling rapid prototyping and design space exploration.

[paper] [pdf] [Code]

OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration

Zhuolun He, Yihang Zuo, Jiaxi Jiang, Haisheng Zheng, Yuzhe Ma, Bei Yu

ACM/IEEE Design Automation Conference (DAC) 2023

Design Rule Checking (DRC) is a critical step in the VLSI design flow that ensures manufacturability of integrated circuits. Traditional DRC tools face scalability challenges with increasing design complexity. This paper presents OpenDRC, an efficient open-source DRC engine that leverages hierarchical GPU acceleration to achieve significant performance improvements. Our approach utilizes the parallel processing capabilities of GPUs and hierarchical design representation to accelerate DRC operations while maintaining accuracy.

[paper] [pdf] [code]

Symmetrical indoor visible light layout optimized by a modified grey wolf algorithm

Yihang Zuo, Bojun Liu, Kunming Shao

Applied Optics (AO) 2022

Visible light communication (VLC) systems require optimal LED placement to ensure uniform illumination and reliable communication. This paper presents a modified grey wolf optimization algorithm for designing symmetrical indoor visible light layouts. The proposed approach optimizes LED positioning to achieve balanced illumination distribution while maintaining communication quality, addressing the challenges of indoor VLC system design.

[paper] [pdf]